Special Issue: 82

Computational cleverness in Complexity of System and Network on Chips in VLSI Communications
for the journal WSEAS Transactions on Systems and Control


Organizer:

Dr. K. Viswanath, IEEE Member, Member of IEEE-SSCS
Block No: 5, 2 nd floor
R.L.Jalappa Institute of Technology
Staff Quarters
Doddaballapur
Bangalore-561203
E-Mail: viswa_kv@pec.edu, vishwanathk@rljit.in
Mobile:-+91-8867431848

Aim:
The Low power and high-speed VLSI chip for communication is the cutting edge technology which brings out the contemporary developments by evolving theories, methods and applications related to computational cleverness in the design of System-on-Chip (SoC), Network-on-Chip (NoC), Bio Signal processing and Internet of Everything’s (IoE) for minimization of cost around the globe. On-chip memories and IoE have become a broad area’s which includes lively forum for the scientific community and industry across the globe to solve diversity of complex problems and intelligent algorithms. The Computational cleverness (CC) explores new directions in probabilistic and statistical models to solve the ever-growing challenges in Low power and high-speed VLSI chips. The CC empowers the users to explore the learning techniques that support to include neural networks, fuzzy systems, evolutionary algorithms, hybrid intelligent systems, uncertain reasoning methods and other machine learning methods. They could also applied for decision making and problem-solving in SoC and NoC for high throughput and low latency. VLSI chips have the capability to solve the complex operations like Neural Networks which can be applied for different computational intelligence prototypes and cloud intelligent algorithms. The special issue on Computational cleverness in Complexity of System and Network on Chips in VLSI Communications includes the latest technology in VLSI communications for effective analysis of optimizations and to fill the gap between academia and industry difficulties

Topics: 

Track1: Computational Cleverness Paradigms
- Low power digital circuits designs
- System/Network on Chips for transmission of Bio-Signal Processing data’s
- Cryptography
- Fuzzy logic and Systems
- Memories designs
- Clock gates techniques
- Power reduction techniques
- Communication protocols

Track 2: Digital Circuits Applications
- Applications of digital circuits
- Verification through Test Vectors
- Physical Design and Testability
- Applications of CC to Healthcare
- Synthesis and Verification
- Timing analysis
- Applications based on IoT solicitations, e.g. smart systems, smart digital systems, and security, health tracking wearable devices like ECG/EEG, weather monitors

Track3: Design for Testing (DFT)
- Fault detections: Struck at 1 and Struck at 0
- Generation of Test Vectors -Verification
- ASIC- Computer Architecture
- DFT Modes-Perspective
- Lock-Up Latch-Implication on Timing
- Two Pillars of DFT: Controllability & Observability
- Dynamics of Scan Testing

Track4: Front End Design for different applications in VLSI & ASIC
- Validations and Verifications
- Design conceptualization
- Chip optimization
- Logical/physical implementation, and design validation and verification
- Floor Planning and Place & Route for digital designs
- System on Chip and Network on Chips
- Different algorithms for effective routing in NoC
- Network Algorithms
- Switching algorithms
- Clock tree synthesis

How to submit:
You can upload your paper via the web site of the particular
WSEAS journal indicating in the Field: "Notes" the title of the Special Issue


Note that the Deadline for Paper submission is 31st December of 2021.
However the organizers review the papers and publish them in a continuous flow. You do not need to wait the acceptance of the other papers in your session to publish your paper. In case that your paper passes the first round of review (some times the second round of review), it can be published if you satisfy the reviewers' comments and remarks and the Editor-in-Chief decides that your paper You do not have to wait the peer review of the other papers in your Session.