Other Articles by Author(s)

G. Durga
M. Meryl Rino

Author(s) and WSEAS

G. Durga
M. Meryl Rino

WSEAS Transactions on Electronics

Print ISSN: 1109-9445
E-ISSN: 2415-1513

Volume 9, 2018

Notice: As of 2014 and for the forthcoming years, the publication frequency/periodicity of WSEAS Journals is adapted to the 'continuously updated' model. What this means is that instead of being separated into issues, new papers will be added on a continuous basis, allowing a more regular flow and shorter publication times. The papers will appear in reverse order, therefore the most recent one will be on top.

Performance Analysis of Single Event Double Upset Immune D and S-R Flip flops

AUTHORS: G. Durga, M. Meryl Rino

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ABSTRACT: The presence of radiation in space environment causes effects in modern electronic devices. This effects range from degradation of performance to functional failures. One of the radiation effects is SEE (Single-event effects). This work presents a design of D and S-R flip flop as variant of the Dual Interlocked storage Cell (DICE) which is tolerant to a single event double upset (SEDU). The design is referred to as modified transistor DICE (TDICE) which uses PMOS and NMOS transistors as a feedback transistors to block the paths that connect a node to the next node. The use of these transistors hardens the cell to tolerate a single event double upset with critical charge at a large value. Extensive simulation results are provided to assess modified TDICE with respect to traditional circuit figures of merit such as number of transistors, power consumption, and delay. The simulation results show the expense of an increased area for the additional transistors, modified TDICE shows a nearly complete tolerance to a single event double upset. All the simulations are done using Tanner EDA tool with 65nm technology

KEYWORDS: D flip flop, DICE, SET, SEU, S-R flip flop, Tanner EDA tool


[1] Rajaei. R, Tabandeh. M and Fazeli. M, 'Low cost soft error hardened latch designs for nanoscale CMOS technology in presence of process variation', Microelectronics Reliability, Vol. 53, No. 6, pp. 1-13, Jun 2013.

[2] Ramin. R., Mahmoud. T. and Mahdi. F, 'Single event multiple upset (SEMU) tolerant latch designs in presence of process and temperature variations', Journal of Circuits, Systems and Computers, Vol.24, No.1, pp. 1-30, Jan 2014

[3] Zhengfeng Huang, Aibin Yan, Huaguo Liang, and Cuiyun Jiang, 'High-performance, lowcost, and highly reliable radiation hardened latch design', Electronics Letters, Vol. 52, No. 2, pp. 139–141, Jan 2016.

[4] Wang. H.B, Li. Y.Q, Chen. L, Li. L.X, Liu. R, Baeg. S, Mahatme. N, Bhuva. B. L, Wen. , S.J, Wong. R and Fung. R, 'An SEU-Tolerant DICE Latch Design With Feedback Transistors', IEEE Transactions on Nuclear Science, Vol.62, No. 2, pp. 548-554, Apr 2015.

[5] Marco d’Alessio, Marco Ottavi and Fabrizio Lombardi, 'Design of a nanometric CMOS memory cell for hardening to a single event with a multiple-node upset', IEEE Transactions on Device and Materials Reliability, vol. 14, No. 1, pp. 127-132, Mar 2014.

[6] Calin.T, Nicolaidis.M and Velazco.R, 'Upset hardened Memory design for Submicron CMOS technology', IEEE Transactions on Nuclear Science, vol. 43, No. 6, pp. 2874– 2878, Dec 1996.

[7] Cha. H and Patel. J. H, 'A logic-level model for α-particle hits in CMOS circuits', IEEE International Conference on Computer Design, pp. 538 – 542, Mar 1993.

[8] Jagannathan. S, Loveless. T. D, Bhuva. B. L, Wen. S. J, Wong. R, Sachdev. M, Rennie. D and Massengill. L.W, 'Single-Event Tolerant Flip-Flop Design in 40-nm Bulk CMOS Technology', IEEE Transactions on Nuclear Science, vol. 58, NO. 6, pp. 3033-3037, Dec 2011.

[9] Loveless. T. D, Jagannathan. S, Reece. T, Chetia. B, Bhuva. B. L, McCurdy. M. W, Massengill. L. W, Wen. S. J, Wong. R and Rennie. D, 'Neutron- and Proton-Induced Single Event Upsets for D- and DICE-Flip/Flop Designs at a 40 nm Technology Node', IEEE Transactions on Nuclear Science, Vol. 58, No. 3, pp.1008-1014, June 2011.

[10] Yang. H.Z and Lin. S.H (Jan 2007), 'Reliable SR latches design using local redundancy', Electronics Letters, Vol. 43 No. 2, pp. 82 – 84.

[11] Messenger. G, 'Collection of charge on junction nodes from ion tracks', IEEE Transactions on Nuclear Science, vol. 29, no. 6, pp. 2024–2031, Nov 1982.

[12] Yang. F.L and Saleh. R.A, 'Simulation and Analysis of Transient Faults in Digital Circuits', IEEE Transactions on Solid State Circuits, Vol. 27, No. 3, pp. 258 – 264, Mar 1992.

[13] Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri and Gwan S Choi., 'Circuit -Level Design Approaches for Radiation-Hard Digital Electronics', IEEE transactions on very large scale integration (VLSI) systems, vol. 17, No. 6, pp. 781-792, June 2009

WSEAS Transactions on Electronics, ISSN / E-ISSN: 1109-9445 / 2415-1513, Volume 9, 2018, Art. #7, pp. 61-68

Copyright © 2018 Author(s) retain the copyright of this article. This article is published under the terms of the Creative Commons Attribution License 4.0

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