Other Articles by Author(s)

Yogita Gajare
Arti Khaparde

Author(s) and WSEAS

Yogita Gajare
Arti Khaparde

WSEAS Transactions on Electronics

Print ISSN: 1109-9445
E-ISSN: 2415-1513

Volume 9, 2018

Notice: As of 2014 and for the forthcoming years, the publication frequency/periodicity of WSEAS Journals is adapted to the 'continuously updated' model. What this means is that instead of being separated into issues, new papers will be added on a continuous basis, allowing a more regular flow and shorter publication times. The papers will appear in reverse order, therefore the most recent one will be on top.

Design and Simulation of First Order One Bit Sigma Delta ADC in 180nm CMOS Technology

AUTHORS: Yogita Gajare, Arti Khaparde

Download as PDF

ABSTRACT: Sigma Delta ADC includes OP-AMP integrator, comparator and d flip-flop. Smoothing operation of OP-AMP integrator with sufficient gain and stability plays a significant role in Sigma Delta ADC for high frequency applications. Low power, Low cost comparator is demanded circuit in a market due to resolution of ADC converter depends on the comparator. Speed and variability of D flip-flop are required in sigma delta ADC to count the number of pulses after comparator. Hence this paper proposed modified zero cancelling method for stability and gain of OP-AMP integrator .This is achieved by modified biasing circuit of series feedback transistor. Resolution of ADC converter is prominently depend on comparator design. Modified comparator circuit appropriates for enhancing gain and for getting low power circuit due to proper biasing of transistor. The paper also aims to simulate Sigma delta ADC using single phase clocked feedback D flip-flop. Sigma Delta ADC is simulated in 180nm CMOS technology in Electric VLSI CAD Tool and TSMC BSIM3 is used as a model library. Supply voltage is 1.8v at 27◦ c temperature and Unity Gain Bandwidth (UGB) =5MHz.

KEYWORDS: OP-AMP, Stability, gain, Comparator, D flip-flop, ADC


[1]. Nowshad Amin,Goh Chit Guan,Ibrahim Ahmad, An Efficient First Order Sigma Delta Modulator Design, Canadian conference on electrical and computer engineering , 2008, ISSN:0840-7789.

[2]. S.S. Chauhan,R.S.Gamad, A New Design of OTA for Sigma-Delta ADC, IEEE UP Section Conference on Electrical Computer and Electronics,2015,ISBN:978-1-4673- 8507-7.

[3]. Puneet Goyal,Sunil Jadhav,Dr.M.Vashisath,Dr.R.Chandel, Study And Performance Analysis Of Two Stage High Speed Operational Using Indirect Compensation, Engineering science and technology: An international Journal, Amplifier , August 2012 Vol.2,No. 4, ISSN:2250-3498.

[4]. Chandra Shankar, Manjeet Kaur, Stability and Bandwidth Enhancement of Two Stage OP-amp using Negative Capcacitance Generation, Inernationsl joural of micro and nano electronics,Circuits and Systems,2(2), 2010,pp.113-118.

[5]. Mohd Haidar Hamzah, Asral Bahari Jambek,Uda Hashim, Design and Analysis of a Two-stage CMOS Op-amp using Silterra’s 0.13 μm Technology, IEEE Symposium on Computer Applications & Industrial Electronics (ISCAIE) , April 7 - 8,2014, Penang, Malaysia.

[6]. Ruud G.H. Eschauzier, Johan H. Huijsing, An Operational Amplifier with Multipath Miller Zero Cancellation for RHP Zero Removal ,solid-state Circuits IEEE Confrence,1993.

[7]. Dr. R.P Singh,Mr. Sunil, Design & Simulation of Second Stage & Three Stage OP-AMP Using 0.35μm CMOS Technology , International Journal of Research and Engineering ,2015,Volume 2, Issue 9, ISSN 2348-7852 (Print) | ISSN 2348-7860.

[8]. J. Mahattanakul, Design Procedure for TwoStage CMOS Operational Amplifiers Employing Current Buffer , IEEE Transactions On Circuits And Systems—Ii: Express Briefs, November 2005, Vol. 52, No. 11.

[9]. Yogita gajare,Arti khaparde, Comparison of D Flip-flops using Variability and Delay Analysis for Sigma Delta ADC ,International journal of Circuits and Electronics,2018,Vol.3,ISSN:2367-8879.

[10]. Himanshu Kumar, Amresh Kumar, Aminul Islam, Comparative Analysis of D FlipFlops in Terms of Delay and its Variability , 4th International Conference on Reliability, Infocom Technologies and Optimization (ICRITO) IEEE, 2015.

[11]. M. Alioto, G. Palumbo, and M. Pennisi, Understanding the effect of process variations on the delay static and domino logic, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., May 2010,vol.18, no. 5, pp. 697–710.

[12]. R. Vaddi, S. Dasgupta, and R. P. Agarwal, Device and circuit co-design robustness studies in the subthreshold logic for ultralow-power applications for 32nm CMOS , IEEE transactions on Electronic Devices, Feb. 2010, vol. 57, no. 3, pp. 654- 664.

[13]. R.Jacob Baker, CMOS Circuit design, layout and simulation, third Edition, Wiley Publication, Chap.5, 2010.

[14]. B.Razavi, Design of Analog CMOS Integrated Circuits, Tata McGraw-Hill, Fourteenth Edition, 2008.

[15]. P.E.Allen and D.R.Holberg, CMOS Analog Circuit Design ,Oxford UniversityPress,2011.

WSEAS Transactions on Electronics, ISSN / E-ISSN: 1109-9445 / 2415-1513, Volume 9, 2018, Art. #1, pp. 1-7

Copyright © 2018 Author(s) retain the copyright of this article. This article is published under the terms of the Creative Commons Attribution License 4.0

Bulletin Board


The editorial board is accepting papers.

WSEAS Main Site