Other Articles by Author(s)

A. Pullareddy
G. Sreenivasulu

Author(s) and WSEAS

A. Pullareddy
G. Sreenivasulu

WSEAS Transactions on Electronics

Print ISSN: 1109-9445
E-ISSN: 2415-1513

Volume 9, 2018

Notice: As of 2014 and for the forthcoming years, the publication frequency/periodicity of WSEAS Journals is adapted to the 'continuously updated' model. What this means is that instead of being separated into issues, new papers will be added on a continuous basis, allowing a more regular flow and shorter publication times. The papers will appear in reverse order, therefore the most recent one will be on top.

Design and Implementation of High Speed Sense Amplifier for SRAM

AUTHORS: A. Pullareddy, G. Sreenivasulu

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ABSTRACT: The Sense amplifier’s sense delay is one important parameter to measure the speed of SRAM memory cell. The sense delay depends on the amplifier reaction time. This delay parameter is more vulnerable to device variations, temperature and supply voltage variations. A latch type voltage controlled sense amplifier considered among all the offered current and voltage sense amplifier types for data sensing from the SRAM cell. The modified conventional latch type voltage controlled coupling capacitor based sense amplifier is implemented to improve the performance of the memory cell. The proposed circuit scheme will provide the reasonable negative voltage at the sense amplifier virtual ground, then the driving capability of the pull down (NMOS) transistors is increased, hence it made the sense amplifier faster. The conventional sense amplifier is compared with proposed coupling capacitor sense amplifier. From the experimental results, it is observed that coupling capacitor based sense amplifier circuit scheme will decrease the sense amplifier reaction time and access the data fast. The result shows, the proposed scheme provides the improvement of sense delay reduction of 198ps at SS/-40º C/1.2v and 18ps at FF/127º C/1.2v process corners at the cost of power consumption.

KEYWORDS: Coupling Capacitor, SRAM cell, Offset, Reaction time.


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WSEAS Transactions on Electronics, ISSN / E-ISSN: 1109-9445 / 2415-1513, Volume 9, 2018, Art. #14, pp. 112-120

Copyright Β© 2018 Author(s) retain the copyright of this article. This article is published under the terms of the Creative Commons Attribution License 4.0

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