Other Articles by Author(s)

Dalia El-Dib

Author(s) and WSEAS

Dalia El-Dib

WSEAS Transactions on Electronics

Print ISSN: 1109-9445
E-ISSN: 2415-1513

Volume 9, 2018

Notice: As of 2014 and for the forthcoming years, the publication frequency/periodicity of WSEAS Journals is adapted to the 'continuously updated' model. What this means is that instead of being separated into issues, new papers will be added on a continuous basis, allowing a more regular flow and shorter publication times. The papers will appear in reverse order, therefore the most recent one will be on top.

Techniques of Low Power Digital Design: A Survey

AUTHORS: Dalia El-Dib

Download as PDF

ABSTRACT: For two decades, low power/energy design has been a major design constraint. The explosion in digital communications and the desire to preserve battery life time, improve system reliability, and reduce cooling costs has pushed for extensive research in low power/energy digital design. In this paper low energy versus low power will be discussed. Then the basics of low power design trends, major techniques and recent challenges will be demonstrated and discussed.

KEYWORDS: Digital Design, low power, energy efficient


[1] G. Moore, “Cramming more components onto integrated circuits,” Electronics Maganize, vol. 38, no. 8, pp. 52–59, 1965.

[2] G. E. Moore et al., “Progress in digital integrated electronics,” in Electron Devices Meeting, vol. 21, 1975, pp. 11–13.

[3] G. E. Moore, “Lithography and the future of moore’s law,” in SPIE’s 1995 Symposium on Microlithography. International Society for Optics and Photonics, 1995, pp. 2–17.

[4] N. N. Tan, D. Li, and Z. Wang, Ultra-low power integrated circuit design. Springer, 2014, vol. 1801466741.

[5] P. R. Panda, B. Silpa, A. Shrivastava, and K. Gummidipudi, Power-efficient system design. Springer Science & Business Media, 2010.

[6] D. A. Patterson and J. L. Hennessy, Computer organization and design: the hardware/software interface. Newnes, 2013.

[7] N. Z. Haron and S. Hamdioui, “Why is cmos scaling coming to an end?” in 2008 3rd International Design and Test Workshop. IEEE, 2008, pp. 98–103.

[8] J. M. Rabaey and M. Pedram, Low power design methodologies. Springer Science & Business Media, 2012, vol. 336.

[9] J. Wu, Y.-L. Shen, K. Reinhardt, H. Szu, and B. Dong, “A nanotechnology enhancement to moore’s law,” Applied Computational Intelligence and Soft Computing, vol. 2013, p. 2, 2013.

[10] A. Pal, Low-Power VLSI Circuits and Systems. Springer, 2014.

[11] Y. Li, “Memory-centric low power digital system design,” Ph.D. dissertation, Rensselaer Polytechnic Institute, 2012.

[12] M. Anis and M. Elmasry, Multi-threshold CMOS digital circuits–managing leakage power. Springer, 2003, vol. 3.

[13] R. Chadha and J. Bhasker, An ASIC Low Power Primer: Analysis, Techniques and Specification. Springer Science & Business Media, 2012.

[14] B. Zhai, D. Blaauw, D. Sylvester, and K. Flautner, “Theoretical and practical limits of dynamic voltage scaling,” in Proceedings of the 41st annual Design Automation Conference. ACM, 2004, pp. 868–873.

[15] J. Kim, F. Gruian, and D. Shin, “Dynamic voltage scaling for low-power hard real-time systems,” in The VLSI handbook, W.-K. Chen, Ed. CRC press, 2016, ch. 18.

[16] V. Sundriyal and M. Sosonkina, “Runtime power-aware energy-saving scheme for parallel applications,” Computer Science Technical Reports, Iowa State University, 2015.

[17] M. D. Wong, “Low power design with multi-vdd and voltage islands,” in 2007 7th International Conference on ASIC. IEEE, 2007, pp. 1325– 1325.

[18] ——, “A low power design methodology with multi -vdd and voltage islands,” Ph.D. dissertation, University of California, 2007.

[19] M. B. Henry, “Emerging power-gating techniques for low power digital circuits,” Ph.D. dissertation, Virginia Tech, 2011.

[20] Z. Abid, D. A. El-Dib, and R. Mudassir, “Modified operand decomposition multiplication for high performance parallel multipliers,” Journal of Circuits, Systems and Computers, p. 1650149, 2016.

[21] D. A. El-Dib and M. I. Elmasry, “Modified register-exchange viterbi decoder for low-power wireless communications,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 51, no. 2, pp. 371–378, 2004.

[22] A. Jayasekar and S. Vimalraj, “Low power digital design using asynchronous logic,” Master’s thesis, San Jos State University, 2011.

[23] M. Joshi and R. Patel, “Performance comparison of different asynchronous design methodologies,” Digital Signal Processing, vol. 8, no. 5, pp. 130–134, 2016.

[24] S. K. Lim, Design for high performance, low power, and reliable 3D integrated circuits. Springer Science & Business Media, 2012.

[25] K. M. Kim, S. Sinha, B. Cline, G. Yeric, and S. K. Lim, “Four-tier monolithic 3d ics: Tier partitioning methodology and power benefit study,” in Proceedings of the 2016 International Symposium on Low Power Electronics and Design. ACM, 2016, pp. 70–75.

[26] K. Pathak and G. T. Arasu, “Design and characterization of shorted gate finfet for low power circuits,” in Electrical, Electronics, Signals, Communication and Optimization (EESCO), 2015 International Conference on. IEEE, 2015, pp. 1–4.

[27] S. Ferwani, S. Khandelwal, and R. Shrivastava, “Low power finfet based operational amplifier with improved gain at 45 nm technology regime,” Journal of Nanoelectronics and Optoelectronics, vol. 11, no. 3, pp. 377–381, 2016.

[28] V. S. Kumar, S. Saravanan, P. Deepa, and S. Priyanka, “Design and implementation of low power finfets using adiabatic logic,” MiddleEast Journal of Scientific Research 24 (Techniques and Algorithms in Emerging Technologies), 2016.

[29] N. Gupta, A. Makosiej, A. Vladimirescu, A. Amara, and C. Anghel, “Ultra-low-power compact tfet flip-flop design for highperformance low-voltage applications,” in 2016 17th International Symposium on Quality Electronic Design (ISQED). IEEE, 2016, pp. 107–112.

[30] H. F. Dadgour and K. Banerjee, “Hybrid nemscmos integrated circuits: A novel strategy for energy-efficient designs,” IET computers & digital techniques, vol. 3, no. 6, pp. 593–608, 2009.

[31] S. Yazdanshenas, B. Khaleghi, P. Ienne, and H. Asadi, “Designing low power and durable digital blocks using shadow nanoelectromechanical relays,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016.

[32] J. L. Munoz-Gamarra, A. Uranga, and ˜ N. Barniol, “Cmos-nems copper switches monolithically integrated using a 65 nm cmos technology,” Micromachines, vol. 7, no. 2, p. 30, 2016.

[33] J. H. Kim, J. Xiang, Z. C.-y. Chen, and S. Kwon, “Nanowire nanoelectromechanical field-effect transistors,” Feb. 25 2016, uS Patent 20,160,056,304.

[34] K. Buch, “Hdl design methods for low-power implementation,” EInfochips, Dec, 2009.

[35] A. Gupta, S. Murgai, A. Gulati, and P. Kumar, “Design and implementation of low power clock gated 64-bit alu on ultra scale fpga,” in ADVANCEMENT IN SCIENCE AND TECHNOLOGY: Proceedings of the 2nd International Conference on Communication Systems (ICCS2015), vol. 1715. AIP Publishing, 2016.

[36] A. A. E. Zarandi, A. S. Molahosseini, L. Sousa, M. Hosseinzadeh, and K. Navi, “Area-delaypower-aware adder placement method for rns reverse converter design,” in 2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS). IEEE, 2016, pp. 223–226.

[37] M. P. Mills, “The cloud begins with coal,” Digital Power Group. Online at: http://www. tech-pundit. com/wpcontent/uploads/2013/07/Cloud Begins With Coal. pdf, 2013.

WSEAS Transactions on Electronics, ISSN / E-ISSN: 1109-9445 / 2415-1513, Volume 9, 2018, Art. #8, pp. 69-78

Copyright © 2018 Author(s) retain the copyright of this article. This article is published under the terms of the Creative Commons Attribution License 4.0

Bulletin Board


The editorial board is accepting papers.

WSEAS Main Site