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Sabrije Osmanaj
Rexhep Selimaj

Author(s) and WSEAS

Sabrije Osmanaj
Rexhep Selimaj

WSEAS Transactions on Electronics

Print ISSN: 1109-9445
E-ISSN: 2415-1513

Volume 8, 2017

Notice: As of 2014 and for the forthcoming years, the publication frequency/periodicity of WSEAS Journals is adapted to the 'continuously updated' model. What this means is that instead of being separated into issues, new papers will be added on a continuous basis, allowing a more regular flow and shorter publication times. The papers will appear in reverse order, therefore the most recent one will be on top.

Simulation and Design of an Integrated Planar Inductor Using Fabrication Technology

AUTHORS: Sabrije Osmanaj, Rexhep Selimaj

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ABSTRACT: This paper presents the conceptions and characterization of integrated planar inductor containing magnetic layers. A novel approach has been used to perform planar magnetic devices by using physical model for integrated planar inductor for 35 μm fabrication technology. According to CMP, C35B3C0 fabrication technology provides three metallic layers; therefore, there is no need to use poly-silicon or diffused underpasses. The metallic -1 layer is used for underpasses. Operation voltage of IC's (Integrated Circuits) fabricated with this technology is 2.5 to 3.6 V. The physical model of the integrated planar inductor is designed using “The Electric VLSI Design”. The purpose of this paper is to present and compare the results of total inductivity of inductors with different number of turns. Grover's expressions are used for calculations. Simulated results for parasitic and resistance capacities for our model are presented in this paper, too.

KEYWORDS: CMOS proces, Planar inductor, Self-inductance, Mutual-inductance


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WSEAS Transactions on Electronics, ISSN / E-ISSN: 1109-9445 / 2415-1513, Volume 8, 2017, Art. #3, pp. 13-20

Copyright © 2017 Author(s) retain the copyright of this article. This article is published under the terms of the Creative Commons Attribution License 4.0

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