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Larissa Soares
Cleonilson Souza

Author(s) and WSEAS

Larissa Soares
Cleonilson Souza

WSEAS Transactions on Communications

Print ISSN: 1109-2742
E-ISSN: 2224-2864

Volume 16, 2017

Notice: As of 2014 and for the forthcoming years, the publication frequency/periodicity of WSEAS Journals is adapted to the 'continuously updated' model. What this means is that instead of being separated into issues, new papers will be added on a continuous basis, allowing a more regular flow and shorter publication times. The papers will appear in reverse order, therefore the most recent one will be on top.

A Practical Approach to Obtain Defect Matrix for Integrated Circuit Testing

AUTHORS: Larissa Soares, Cleonilson Souza

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ABSTRACT: Testing of integrated circuits (ICs) is always a challenge because the continuous miniaturization process and consequently increase of transistor density in microelectronic industry. Nowadays, the industry has to handle with defects that traditional testing approaches can not detect. The result of this imprecise testing process is the increase number of defective ICs that reach the end consumer. To improve the quality of IC testing, a new approach of fault modeling is being adopted which is not based on transistor or logic gate level, but in the IC layout perspective itself. This paper describes the meaning of testing based on layout perspective, particularly, Cell-Aware Testing (CAT) methodology, and a practical approach to obtain the matrix of defects, in which is the set of test patterns to each modelled fault coming from CAT, and that is the CAT’s main result. Experimental simulation results show the matrix of defects obtained for a specific standard cell that can be immediately used by an ATPG.

KEYWORDS: Defect, Fault-model, Layout-perspective, Defect insertion


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WSEAS Transactions on Communications, ISSN / E-ISSN: 1109-2742 / 2224-2864, Volume 16, 2017, Art. #34, pp. 315-321

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