AUTHORS: P. Balasubramanian, K. Prasad
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ABSTRACT: This paper presents the designs of asynchronous early output dual-bit full adders without and with redundant logic (implicit) corresponding to homogeneous and heterogeneous delay-insensitive data encoding. For homogeneous delay-insensitive data encoding only dual-rail i.e. 1-of-2 code is used, and for heterogeneous delay-insensitive data encoding 1-of-2 and 1-of-4 codes are used. The 4-phase return-to-zero protocol is used for handshaking. To demonstrate the merits of the proposed dual-bit full adder designs, 32-bit ripple carry adders (RCAs) are constructed comprising dual-bit full adders. The proposed dual-bit full adders based 32-bit RCAs incorporating redundant logic feature reduced latency and area compared to their non-redundant counterparts with no accompanying power penalty. In comparison with the weakly indicating 32-bit RCA constructed using homogeneously encoded dual-bit full adders containing redundant logic, the early output 32-bit RCA comprising the proposed homogeneously encoded dual-bit full adders with redundant logic reports corresponding reductions in latency and area by 22.2% and 15.1% with no associated power penalty. On the other hand, the early output 32-bit RCA constructed using the proposed heterogeneously encoded dual-bit full adder which incorporates redundant logic reports respective decreases in latency and area than the weakly indicating 32-bit RCA that consists of heterogeneously encoded dual-bit full adders with redundant logic by 21.5% and 21.3% with nil power overhead. The simulation results obtained are based on a 32/28nm CMOS process technology.
KEYWORDS: Asynchronous design, Digital circuits, Full adder, Ripple carry adder, Indication, Early output, Standard cells, CMOS
REFERENCES:
[1]S. Goel, A. Kumar, M.A. Bayoumi, “Design of robust, energy-efficient full adders for deep submicrometer design using hybrid-CMOS logic style,” IEEE Trans. on VLSI Systems, vol. 14, no. 12, pp. 1309-1321, 2006.
[2]P. Balasubramanian, N.E. Mastorakis, “High speed gate level synchronous full adder designs,” WSEAS Trans. on Circuits and Systems, vol. 8, no. 2, pp. 290-300, 2009.
[3]P. Balasubramanian, N.E. Mastorakis, “A delay improved gate level full adder design,” Proc. 3rd European Computing Conf., pp. 97-102, 2009.
[4]P. Balasubramanian, N.E. Mastorakis, “A low power gate level full adder module,” Proc. 3rd Intl. Conf. on Circuits, Systems and Signals, Invited Paper, pp. 246-248, 2009.
[5]C.L. Seitz, “System Timing,” in Introduction to VLSI Systems, C. Mead and L. Conway (Editors), pp. 218-262, Addison-Wesley, Reading, Massachusetts, USA, 1980.
[6]A.J. Martin, “Asynchronous datapaths and the design of an asynchronous adder,” Formal Methods in System Design, vol. 1, no. 1, pp. 117- 137, 1992.
[7]W.B. Toms, D.A. Edwards, “Efficient synthesis of speed independent combinational logic circuits,” Proc. 10th Asia and South Pacific Design Automation Conf., pp. 1022-1026, 2005.
[8]B. Folco, V. Bregier, L. Fesquet, M. Renaudin, “Technology mapping for area optimized quasi delay insensitive circuits,” Proc. Intl. Conf. on VLSI-SoC, pp. 146-151, 2005.
[9]P. Balasubramanian, D.A. Edwards, “A delay efficient robust self-timed full adder,” Proc. 3rd IEEE Intl. Design and Test Workshop, pp. 129- 134, 2008.
[10] P. Balasubramanian, D.A. Edwards, “Self-timed full adder designs based on hybrid input encoding,” Proc. 12th IEEE Symp. on Design and Diagnostics of Electronic Circuits and Systems, pp. 56-61, 2009.
[11] P. Balasubramanian, “A robust asynchronous early output full adder,” WSEAS Trans. on Circuits and Systems, vol. 10, no. 7, pp. 221-230, 2011.
[12] P. Balasubramanian, “A latency optimized biased implementation style weak-indication selftimed full adder,” Facta Universitatis, Series: Electronics and Energetics, vol. 28, no. 4, pp. 657-671, 2015.
[13] P. Balasubramanian, “An asynchronous early output full adder and a relative-timed ripple carry adder,” WSEAS Trans. on Circuits and Systems, vol. 15, pp. 91-101, 2016.
[14] P. Balasubramanian, S. Yamashita, “Area/latency optimized early output asynchronous full adders and relative-timed ripple carry adders,” SpringerPlus, vol. 5:440, pages 26, 2016.
[15] P. Balasubramanian, K. Prasad, “Early output hybrid input encoded asynchronous full adder and relative-timed ripple carry adder,” Proc. 14th Intl. Conf. on Embedded Systems, Cyber-physical Systems, and Applications, pp. 62-65, 2016.
[16] P. Balasubramanian, K. Prasad, N.E. Mastorakis, “A standard cell based synchronous dual-bit adder with embedded carry look-ahead,” WSEAS Trans. on Circuits and Systems, vol. 9, no. 12, pp. 736-745, 2010.
[17] P. Balasubramanian, D.A. Edwards, “Dual-sum single-carry self-timed adder designs,” Proc. IEEE Computer Society Annual Symp. on VLSI, pp. 121-126, 2009.
[18] P. Balasubramanian, D.A. Edwards, “Heterogeneously encoded dual-bit self-timed adder,” Proc. IEEE Ph.D. Research in Microelectronics and Electronics Conf., pp. 120- 123, 2009.
[19] J. Sparsø, S. Furber, Principles of Asynchronous Circuit Design: A Systems Perspective, Kluwer Academic Publishers, Boston, MA, USA, 2001.
[20] T. Verhoeff, “Delay-insensitive codes – an overview,” Distributed Computing, vol. 3, no. 1, pp. 1-8, 1988.
[21] C. Jeong, S.M. Nowick, “Optimization of robust asynchronous circuits by local input completeness relaxation,” Proc. Asia and South Pacific Design Automation Conf., pp. 622-627, 2007.
[22] P. Balasubramanian, K. Prasad, N.E. Mastorakis, “Robust asynchronous implementation of Boolean functions on the basis of duality,” Proc. 14th WSEAS Intl. Conf. on Circuits, pp. 37-43, 2010.
[23] P. Balasubramanian, Self-Timed Logic and the Design of Self-Timed Adders, PhD thesis, The University of Manchester, 2010.
[24] A.J. Martin, “The limitation to delayinsensitivity in asynchronous circuits,” Proc. 6th MIT Conf. on Advanced Research in VLSI, pp. 263-278, 1990.
[25] B. Bose, “On unordered codes,” IEEE Trans. on Computers, vol. 40, no. 2, pp. 125-131, 1991.
[26] S.J. Piestrak, T. Nanya, “Towards totally selfchecking delay-insensitive systems,” Proc. 25th Intl. Symp. on Fault-Tolerant Computing, pp. 228-237, 1995.
[27] V.I. Varshavsky (Ed.), Self-Timed Control of Concurrent Processes: The Design of Aperiodic Logical Circuits in Computers and Discrete Systems, Chapter 4: Aperiodic Circuits, pp. 77-85, (Translated from the Russian by A.V. Yakovlev), Kluwer Academic Publishers, 1990.
[28] P. Balasubramanian, D.A. Edwards, “Efficient realization of strongly indicating function blocks,” Proc. IEEE Computer Society Annual Symp. on VLSI, pp. 429-432, 2008.
[29] P. Balasubramanian, D.A. Edwards, “A new design technique for weakly indicating function blocks,” Proc. 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, pp. 116-121, 2008.
[30] P. Balasubramanian, N.E. Mastorakis, “Global versus local weak-indication self-timed function blocks – a comparative analysis,” Proc. 10th Intl. Conf. on Circuits, Systems, Signal and Telecommunications, pp. 86-97, 2016.
[31] C.F. Brej, J.D. Garside, “Early output logic using anti-tokens,” Proc. 12th Intl. Workshop on Logic and Synthesis, pp. 302-309, 2003.
[32] P. Balasubramanian, “Comments on “Dual-rail asynchronous logic multi-level implementation”,” Integration, the VLSI Journal, vol. 52, no. 1, pp. 34-40, 2016.
[33] P. Balasubramanian, R. Arisaka, H.R. Arabnia, “RB_DSOP: A rule based disjoint sum of products synthesis method,” Proc. 12th Intl. Conf. on Computer Design, pp. 39-43, 2012.
[34] P. Balasubramanian, N.E. Mastorakis, “A set theory based method to derive network reliability expressions of complex system topologies,” Proc. Applied Computing Conf., pp. 108-114, 2010.
[35] P. Balasubramanian, D.A. Edwards, “Self-timed realization of combinational logic,” Proc. 19th Intl. Workshop on Logic and Synthesis, pp. 55-62, 2010.
[36] Synopsys SAED_EDK32/28_CORE Databook, Revision 1.0.0, 2012.
[37] P. Balasubramanian, D.A. Edwards, W.B. Toms, “Redundant logic insertion and latency reduction in self-timed adders,” VLSI Design, vol. 2012, Article ID 575389, pages 13, 2012.
[38] P. Balasubramanian, N.E. Mastorakis, “QDI decomposed DIMS method featuring homogeneous/heterogeneous data encoding,” Proc. Intl. Conf. on Computers, Digital Communications and Computing, pp. 93-101, 2011.
[39] P. Balasubramanian, “Asynchronous carry select adders,” Engineering Science and Technology, an Intl. Journal, 2017, DOI: http://dx/doi.org/10.1016/j.jestch.2017.02.003
[40] P. Balasubramanian, D.A. Edwards, W.B. Toms, “Self-timed multi-operand addition,” Intl. Jour. of Circuits, Systems and Signal Processing, vol. 6, no. 1, pp. 1-11, 2012.