AUTHORS: Allam Abumwais, Abdulkarim Ayyad
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ABSTRACT: A symmetric multi-core processor is a chip which integrates a number of processors (cores). Each core has its own local memory which is accessible by its core only. The cores share and equally access a shared memory. The multi-core processors suffer from the delay caused by the contention among the cores to access the shared memory. Also, a bigger delay results from the cache coherence operations, where each core must update other cores on any change it makes on a shared variable. This is accomplished by broadcasting the change to the rest of the cores. In 2014 the authors completed, tested and verified an organization of a multi-port content addressable memory (MPCAM) which, if used as a shared memory, it allows all the cores of the processor to access it simultaneously without the need for queuing and arbitration. The access time is the same as that of accessing the core’s private memory. The organization of this memory guarantees the cache coherence automatically and eliminates the need for cache coherence operations. This is an unprecedented result. This architecture represents a whole solution to the long standing problem of latency due to contention and cache coherence operations in multi-core (formerly multiprocessor) system
KEYWORDS: Multi-core, shared cache, contention, cache coherence, dual port CAM, multi-port content addressable memory (MPCAM).
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