AUTHORS: Liu De, Wang Mingjiang

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ABSTRACT: This paper presents an architecture of a triple-mode floating-point adder that supports higher precision and parallel lower precision addition. The proposed design can work in three modes: four parallel single precision or two parallel double precision or one quadruple precision addition/subtraction. The proposed triple-mode adder’s parallel computation in lower precision can be applied in SIMD application to accommodate 3D graphics, video conferencing and multimedia fields while its high precision computation can be applied in scientific applications such as supernova simulations, climate modeling and etc. To improve the performance of the triple-mode floating-point adder, the design is implemented with the improved two-path algorithm in combinational and pipeline form. To compare area, power and worst-case latency, single-mode single, double, quadruple and dual-mode quadruple precision floating-point adders are also implemented using the similar techniques. These adders and the triple-mode adder are tested and verified through extensive simulation and then synthesized with 65nm manufacture process. The synthesis results show that the proposed triple-mode floating-point adder requires 10-16% more delay than a single-mode quadruple precision adder and saves 47-52% area compared to the combination of four single, two double and one quadruple precision adders.

KEYWORDS: floating-point adder, floating-point arithmetic, triple-mode adder

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