AUTHORS: Sabrije Osmanaj, Rexhep Selimaj
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ABSTRACT: This paper presents the conceptions and characterization of integrated planar inductor containing magnetic layers. A novel approach has been used to perform planar magnetic devices by using physical model for integrated planar inductor for 35 μm fabrication technology. According to CMP, C35B3C0 fabrication technology provides three metallic layers; therefore, there is no need to use poly-silicon or diffused underpasses. The metallic -1 layer is used for underpasses. Operation voltage of IC's (Integrated Circuits) fabricated with this technology is 2.5 to 3.6 V. The physical model of the integrated planar inductor is designed using “The Electric VLSI Design”. The purpose of this paper is to present and compare the results of total inductivity of inductors with different number of turns. Grover's expressions are used for calculations. Simulated results for parasitic and resistance capacities for our model are presented in this paper, too.
KEYWORDS: CMOS proces, Planar inductor, Self-inductance, Mutual-inductance
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