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Kaustubh Gaikwad
Mahesh Chavan



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Kaustubh Gaikwad
Mahesh Chavan


WSEAS Transactions on Electronics


Print ISSN: 1109-9445
E-ISSN: 2415-1513

Volume 8, 2017

Notice: As of 2014 and for the forthcoming years, the publication frequency/periodicity of WSEAS Journals is adapted to the 'continuously updated' model. What this means is that instead of being separated into issues, new papers will be added on a continuous basis, allowing a more regular flow and shorter publication times. The papers will appear in reverse order, therefore the most recent one will be on top.



Design and Implementation of Digital Butterworth IIR Filter Using Xilinx System Generator for Noise Reduction in ECG Signal

AUTHORS: Kaustubh Gaikwad, Mahesh Chavan

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ABSTRACT: Application Specific Integrated Circuits (ASICs) and Digital Signal Processors are generally used for implementing digital filters. Now days in the advances in technology leads to use of field programmable Gate Array (FPGA) for the implementation of Digital Filters. The Present paper deals with Design and implementation of digital IIR Butterworth filter using Xilinx System Generator. The Quantization and Overflow are main crucial parameters while designing the filter on FPGA and that need to be consider for getting the stability of the filter. As compare to the conventional DSP the speed of the system is increased by implementation on FPGA. Digital Butterworth filter first designed analytically for the desired Specifications and simulated using Simulink in Matlab environment. This paper also proposes the method to implement Digital IIR Butterworth Filter by using Xilinx system generator. The filer has shown good performance for noise removal in ECG Signal

KEYWORDS: Xilinx System Generator, Butterworth Filter, noise Reduction

REFERENCES:

[1] Michael Francis, Infinite Impulse Response Filter Structures in Xilinx FPGAs Xilinx WP330 (v1.2) August 10, 2009. Figure 10: pole zero Diagram Figure 11: Round Off Noise power Spectrum

[2] C. Saritha, V. Sukanya, Y. Narasimha Murthy ECG Signal Analysis Using Wavelet Transforms, Bulg. J. Phys. 35 (2008) 6877.

[3] L. Cromwell, F.J. Weibell, E.A. Pfeiffer (2005) Biomedical Instrumentation and Measurements, Prentice Hall of India, New Delhi.

[4] Harish V. Dixit, Dr. Vikas Gupta, IIR filters using Xilinx System Generator for FPGA Implementation, International Journal of Engineering Research and Applications Vol. 2, Issue 5, September- October 2012, pp.303-307.

[5] Anurag Aggarwal, Astha Satija, Tushar Nagpal, FIR Filter Designing using Xilinx System Generator, International Journal of Computer Applications Volume 68 No.11, April 2013.

[6] Kumudini Sahu, Rahul Sinha, FIR Filter Designing using MATLAB Simulink and Xilinx system Generator International Research Journal of Engineering and Technology (IRJET) Volume: 02 Issue: 08 Nov-2015.

[7] Patel, S.Design and Implementation of 31-order FIR Low-pass Filter using Modified Distributed Figure 12: Input Output waveforms of digital filter Figure 13: RTL Schematic 1 Arithmetic based on FPGA International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering Vol. 2, Issue 10, ISSN: 2320 3765.

[8] Ayesha Firdous, Dr.B.Rajan, A Comparative Study of Pipelining Techniques for Recursive Filter Implemented in FPGA, International Journal of Scientific & Engineering Research, Volume 5, Issue 4, April-2014 pp.330-333.

[9] Chi-Jui Chou, Satish Mohanakrishnan, Joseph B.Evans,FPGA Implementation of Digital Filters,, Proc.ICSPAT93.

[10] Emmanuel S. Kolawole, Warsame H.Ali, Penrose Cofie, John Fuller, C. Tolliver, Pamela Obiomon, Design and Implementation of LowPass, High-Pass and Band-Pass Finite Impulse Response (FIR) Filters Using FPGA Circuits and Systems, 2015, 6, 30-48

[11] Sushmitha.C, Swathy.R, Veena Devi.S, Esther Jeba Rani.S.A, Nagaraju.N , Design and Simulation of FIR Filter, International Journal of Innovative Research in Science, Engineering and Figure 14: RTL Schematic 2 Technology,Volume 5, Special Issue 2, March 2016, pp 241-245.

[12] Shahnam Mirzaei, Anup Hosangadi, Ryan Kastner , FPGA Implementation of High Speed FIR Filters Using Add and Shift Method International Conference on Computer Design, pp 308- 313.

[13] Shahnam Mirzaei, Anup Hosangadi, Ryan Kastner , FPGA Implementation of High Speed FIR Filters Using Add and Shift Method International Conference on Computer Design, pp 308- 313.

[14] Sweety Kashyap, Mukesh Maheshwari, Implementation of High Performance FIR Filter Using Low Power Multiplier and Adder Int. Journal of Engineering Research and Applications Vol. 4, Issue 1( Version 1), January 2014, pp.177-181.

WSEAS Transactions on Electronics, ISSN / E-ISSN: 1109-9445 / 2415-1513, Volume 8, 2017, Art. #2, pp. 8-12


Copyright © 2017 Author(s) retain the copyright of this article. This article is published under the terms of the Creative Commons Attribution License 4.0

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