AUTHORS: G. Sambasiva Rao, Pattan Vaseem Ali Khan
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ABSTRACT: This paper presents the design style and analysis of ultra-low power adiabatic 4-bit, 8-bit adder-subtractors and also 3-bit, 5-bit BEC (binary to excess-1 converter) based on ECRL (Efficient Charge Recovery Logic) and PFAL (Positive Feedback Adiabatic Logic) logic families which works with the professional four phase power clock. These styles have the profit of energy saving as it reuse the certain amount of the energy by recycling from the load capacitance thus reduces the energy dissipation. MOS level-11 Tanner-spice simulation has been used for the design of Energy saving adiabatic circuits with consideration to particular frequencies with the different load capacitance, and different supply voltages. In analysis, two logic families, ECRL (Efficient Charge Recovery Logic) and PFAL (Positive Feedback Adiabatic Logic) are compare with conventional CMOS logic for Incrementors and adders. Also comparison of ECRL (Efficient Charge Recovery Logic) and PFAL (Positive Feedback Adiabatic Logic) is done. In the analysis it has found that adiabatic is superior for low power applications in Cryptographic hardware for example smart cards, Digital Signal processing system and embedded systems at particular frequency choice.
KEYWORDS: Adiabatic Techniques, BEC (binary to excess-1 converter), Adder-Subtractor, Positive Feedback Adiabatic Logic (PFAL), Efficient Charge Recovery Logic (ECRL), Power Clock, Low Power System
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