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Yurin Jin
Seongik Cho
Minwoong Lee



Author(s) and WSEAS

Yurin Jin
Seongik Cho
Minwoong Lee


WSEAS Transactions on Circuits and Systems


Print ISSN: 1109-2734
E-ISSN: 2224-266X

Volume 16, 2017

Notice: As of 2014 and for the forthcoming years, the publication frequency/periodicity of WSEAS Journals is adapted to the 'continuously updated' model. What this means is that instead of being separated into issues, new papers will be added on a continuous basis, allowing a more regular flow and shorter publication times. The papers will appear in reverse order, therefore the most recent one will be on top.


Volume 16, 2017



Small Area DAC Using SC Integrator for SAR ADC

AUTHORS: Yurin Jin, Seongik Cho, Minwoong Lee

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ABSTRACT: A successive approximation register(SAR) analog-to-digital converter(ADC) is widely used because of its relatively short conversion time and small size. However, a SAR ADC requires a DAC of the same resolution, resulting in a larger area. To solve this problem, a DAC that does not increase in area as resolution increases is needed. This paper presents SAR ADC and DAC using Switched Capacitor(SC) integrator. This DAC 's area is independent of resolution and ADC is no need to a sample and hold circuit because it uses an SC integrator. The operation of this ADC is similar to a charge-redistribution based SAR ADC. The reference voltage is generated by charge redistribution of the SC integrator input capacitor and the reference capacitor, and the DAC voltage is generated by accumulating the generated voltage on the output capacitor of the SC integrator. The proposed SAR ADC was designed using TSMC 0.18μm CMOS high voltage technology, occupies on chip area of 0.316mm2. At 5V supply and 100kS/s, the simulated SNDR and ENOB are 53.7dB and 8.63bit. Considering the good DNL, a higher resolution ADC can be designed with the same area.

KEYWORDS: Analog-to-digital converter, Successive approximation register, Switched Capacitor integrator, SAR ADC, Digital-to-Analog converter, Charge-redistribution based SAR ADC, Sample and Hold circuit

REFERENCES:

[1] Seon-Kyoo Lee, Seung-Jin Park, Hong-June Park, Jae-Yoon Sim, A 21 fJ/Conversion-Step 100 kS/s 10-bit ADC With a Low-Noise TimeDomain Comparator for Low-Power Sensor Interface, IEEE Journal of Solid-State Circuits, Vol.46, No.3, 2011, pp. 651-659.

[2] Xiucheng Zhou, Ying Zhang, Yun S u, An 8-bit 35-MS/s Successive Approximation Register ADC, IEEE Journal of Solid-State Circuits, 2015, pp. 531-533.

[3] Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin, A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure, IEEE Journal of Solid-State Circuits, Vol.45, No.4, 2010, pp. 731-740.

[4] Behzad Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill Education, 2000.

[5] Phillip E. Allen, Douglas R. Holberg, CMOS Analog Circuit Design Second Edition, OXFORD, 2002.

[6] You-Kuang Chang, Chao-Shiun Wang, ChorngKuang Wang, A 8-bit 500-KS/s low power SAR ADC for bio-medical applications, Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian, 2007, pp. 228-231.

[7] E. Atkin, D. Normanov, Area-efficient lowpower 8-bit 20-MS/s SAR ADC in 0.18μm CMOS, Microelectronics Proceedings - MIEL 2014, 2014 29th International Conference on, 2014, pp. 451-454.

[8] Wen Cheng Lai, Jhin Fang Huang, Cheng Gu Hsieh, An 8-bit 20 MS/s successive approximation register analog-to-digital converter for wireless intelligent control and information processing, Intelligent Control and Information Processing (ICICIP), 2014 Fifth International Conference on, 2014, pp. 115-117.

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 16, 2017, Art. #9, pp. 74-78


Copyright © 2017 Author(s) retain the copyright of this article. This article is published under the terms of the Creative Commons Attribution License 4.0

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