Plenary Lecture

Heterogeneous Reconfigurable Chip Multiprocessors for Embedded Systems

Professor Sotirios G. Ziavras
Associate Chair of ECE (in charge of Graduate Programs)
Director of the Computer Architecture and Parallel Processing Laboratory (CAPPL)
Department of Electrical and Computer Engineering (ECE)
New Jersey Institute of Technology
Newark, New Jersey
U.S.A.
E-mail: ziavras@adm.njit.edu

Abstract: Chip multiprocessing has recently become a common practice in processor design. With ever increasing concerns for energy consumption, performance-energy trade-offs are often necessary, especially in the design of real-time embedded systems. Multiprocessor heterogeneity is a successful design paradigm for high performance and energy conservation with embedded systems. Performance and energy analyses will be presented for an in-house developed FPGA*- based mixed-mode heterogeneous chip multiprocessor, where the SIMD (Single-Instruction, Multiple-Data) and MIMD (Multiple-Instruction, Multiple-Data) parallel computing modes can be realized simultaneously or distinctly. The presented performance-energy trade-off techniques are based on the observation that SIMD and MIMD tasks involve substantially different amounts of computation and communication with different execution time and energy behaviors. Experimental results on Xilinx FPGAs demonstrate the effectiveness of the proposed approach.

To conserve space and power as well as to incorporate dynamic adaptability in embedded systems, it is important to utilize hardware components as best as possible. The hardware customization of application kernels reduces the execution time and potentially the power consumption. Reconfiguring the same hardware to facilitate various customized kernels as execution proceeds greatly reduces the space requirements. When the kernel execution is carefully scheduled considering also the reconfiguration overheads, the obtained performance gain can offset such overheads. A policy and experiments will be presented of customizing and reconfiguring multiprocessor hardware for embedded benchmark kernels implemented on FPGAs. The results reveal substantial performance improvement and resource conservation.

* FPGA: Field-Programmable Gate Array


Brief Biography of the Speaker:
Dr. Sotirios G. Ziavras received the Diploma in Electrical Engineering from the National Technical University of Athens, Greece, in 1984, the M.Sc. in Computer Engineering from Ohio University in 1985, and the Ph.D. in Computer Science from George Washington University (GWU) in 1990. He was a Distinguished Graduate Teaching Assistant and Research Assistant at GWU, and also received the Richard Merwin Ph.D. Fellowship.

He was with the Center for Automation Research at the University of Maryland, College Park, from 1988 to 1989 focusing on supercomputing. He was a visiting Professor at George Mason University in Spring 1990. He joined in Fall 1990 the Electrical and Computer Engineering Department at NJIT as an Assistant Professor. He is currently a Professor at NJIT, with joint appointments in the Electrical and Computer Engineering, and Computer Science Departments. He also serves as the Associate Chair for Graduate Studies in ECE.

He received the National Science Foundation (NSF) Research Initiation Award in 1991. In 1996 he lead an NSF/DARPA/NASA-funded New Millennium Computing Point Design project for PetaFLOPS computing. He has received research grants in excess of $2.5M. He has served as an Associate Editor of the Pattern Recognition journal and serves regularly as a member of Conference Program Committees.

He is the author of about 140 scientific papers. He is listed, among others, in Who's Who in Science and Engineering, Who's Who in America, Who's Who in the World, and Who's Who in the East. His main research interests are reconfigurable computing, high-performance computing (architectures and applications), computer architecture and embedded systems.