Plenary Lecture

Design Challenges and Opportunities of the “End of Scaling” Nanoscale CMOS

Prof. Ching-Te Chuang
IBM T. J. Watson Research Center,
Yorktown Heights, NY 10598, U.S.A
Phone: +1-914-945-3596,
Fax: +1-914-945-1358

E-mail: ctchuang@us.ibm.com

Abstract: This presentation reviews the challenges and opportunities of high-performance digital design in the “End of Scaling” nanoscale CMOS technologies. The device structure evolution, material enhancement, and major design challenges are discussed. Examples of logic circuit and SRAM design techniques to overcome the challenges and to mitigate various performance/reliability constraints in conventional planar CMOS technology are given. Scaled/emerging technologies such as scaled PD/SOI, UT/SOI, strained-Si channel device, hybrid orientation technology, and multi-gate FinFET are addressed with particular emphases on the implications and impacts on circuit design. Finally, novel logic circuit, SRAM, and power-gating schemes exploiting unique structures and properties of emerging devices are discussed.

Brief Biography of the Speaker:
Dr. Chuang received the B.S.E.E. from National Taiwan University, Taipei, Taiwan in 1975 and Ph.D. degree in Electrical Engineering from University of California, Berkeley, CA in 1982.
He joined the IBM T. J. Watson Research Center, Yorktown Heights, NY in 1982, and is currently Manager of the High-Performance Circuit Group. Since 1993, his group has been primarily responsible for the circuit design of IBM’s high-performance CMOS microprocessors for enterprise servers, PowerPC workstations, and game/media processors. Since 1996, he has been leading the efforts in evaluating and exploring scaled/emerging technologies, such as PD/SOI, UT/SOI, strained-Si devices, hybrid orientation technology, and multi-gate/FinFET devices, for high-performance logic and SRAM applications.
Dr. Chuang is a Fellow of IEEE. He has authored or coauthored over 250 papers. He holds 21 U.S. patents with another 19 pending.