Plenary Lecture

Fault Tolerant Systems Design in VLSI using Data Compression under Constraints of Failure Probabilities – Overview and Status

Professor Sunil R. Das
School of Information Technology and Engineering, Faculty of Engineering
University of Ottawa, Ottawa, Ontario K1N 6N5, Canada
and
Department of Computer and Information Science, College of Arts and Sciences
Troy University, Montgomery, AL 36103, U. S. A.

Abstract: The realization of space-efficient support hardware for built-in self-testing (BIST) is of critical importance in the design and manufacture of VLSI circuits. Novel approaches to designing aliasing-free space compaction hardware were recently proposed in the context of testing cores-based system-on-chip (SOC) for single stuck-line faults, extending the well-known concepts of conventional switching theory, specifically those of cover table and frequency ordering commonly utilized in the simplification of switching functions, and of compatibility relation as used in the minimization of incomplete sequential machines, based on optimal generalized sequence mergeability, as developed and utilized by the author and his coworkers in earlier works.
Embedded cores-based design paradigm has evolved from the necessity to increase design productivity and decrease time-to-market, but as a result has created numerous challenging problems for the test design community. Keeping in view the many formidable issues that arise in testing these cores-based SOCs, this lecture will provide a brief overview on the general methodology of built-in self-test (BIST) in the context of embedded cores-based system chips, as is widely used in today’s many commercial products with remarkable success, emphasizing the basic philosophy of the technique, test pattern generation procedures, output compaction schemes, test implementation and evaluation methods, with impact on a wide spectrum of issues facing the testing community at the moment.
Also, with details of the different algorithms developed in the implementation of the approaches to designing zero-aliasing space compactors, the lecture will provide the mathematical basis of selection criteria for merger of an optimal number of outputs of the CUT to achieve maximum compaction ratio in the design, along with some results from simulation experiments conducted on ISCAS 85 combinational and ISCAS 89 full-scan sequential benchmark circuits, with simulation programs ATALANTA, FSIM, and HOPE.

Brief Biography of the Speaker:
Sunil R. Das (M'70-SM'90-F'94-LF'04) is an Emeritus Professor of Electrical and Computer Engineering at the School of Information Technology and Engineering, University of Ottawa, Ottawa, ON, Canada and a Professor of Computer and Information Science, Troy University, Montgomery, AL, USA. He holds a B.Sc. (Honors) in Physics and an M.Sc. (Tech) and a Ph.D. in Radiophysics and Electronics from the University of Calcutta, Calcutta, West Bengal, India. He previously held academic and research positions with the Department of Electrical Engineering and Computer Sciences, Computer Science Division, University of California, Berkeley, CA, the Center for Reliable Computing (CRC), Computer Systems Laboratory, Department of Electrical Engineering, Stanford University, Stanford, CA (on sabbatical leave), the Institute of Computer Engineering, National Chiao Tung University, Hsinchu, Taiwan, ROC, and the Center of Advanced Study (CAS), Institute of Radiophysics and Electronics, University of Calcutta.
Dr Das has published around 300 papers in the areas of switching and automata theory, digital logic design, threshold logic, fault-tolerant computing, built-in self-test with emphasis on embedded cores-based system-on-chip (SOC), microprogramming and microarchitecture, microcode optimization, applied theory of graphs, and combinatorics. He served in the Technical Program Committees and Organizing Committees of many IEEE and non-IEEE International Conferences, Symposia, and Workshops, and also acted as session organizer, session chair, and panelist.
Dr Das was elected one of the delegates of the prestigious GOOD PEOPLE, GOOD DEEDS of the Republic of China in 1981 in recognition of his outstanding contributions in the field of research and education. He is listed in the MARQUIS WHO'S WHO Biographical Directory of the Computer Graphics Industry, Chicago, IL (First Edition, 1984).
Dr Das served as the Managing Editor of the IEEE VLSI Technical Bulletin, a publication of the IEEE Computer Society Technical Committee (TC) on VLSI since its very inception, and also was an Executive Committee Member of the IEEE Computer Society Technical Committee (TC) on VLSI. Dr Das also served as an Associate Editor of the IEEE Transactions on Systems, Man, and Cybernetics (subsequently Part A, Part B, and Part C) since 1991 until very recently. He is currently an Associate Editor of the IEEE Transactions on Instrumentation and Measurement, an Associate Editor of the International Journal of Computers and Applications published by Acta Press, Calgary, AB, a Regional Editor for Information Technology Journal, an official publication of Asian Network for Scientific Information, and a former Member of the Editorial Board and a Regional Editor for Canada of the VLSI Design: An International Journal of Custom-Chip Design, Simulation and Testing published by Gordon and Breach Science Publishers, Inc., NY. Dr Das is a former Administrative Committee (ADCOM) Member of the IEEE Systems, Man, and Cybernetics Society, a former Associate Editor of the IEEE Transactions on VLSI Systems (for two consecutive terms), a former Associate Editor of the SIGDA Newsletter, the publication of the ACM Special Interest Group on Design Automation, a former Associate Editor of the International Journal of Computer Aided VLSI Design published by Ablex Publishing Corporation, Norwood, NJ, and a former Associate Editor of International Journal of Parallel and Distributed Systems and Networks published by Acta Press. Dr Das also served as the Co-Chair of the IEEE Computer Society Students Activities Committee from Region 7 (Canada). He was the Associate Guest Editor of the IEEE Journal of Solid-State Circuits Special Issues on Microelectronic Systems (Third and Fourth Special Issues), and Guest Editor of the International Journal of Computer Aided VLSI Design (September 1991) as well as VLSI Design: An International Journal of Custom-Chip Design, Simulation and Testing (March 1993, September 1996, and December 2001), Special Issues on VLSI Testing. He also Guest Edited jointly with Rochit Rajsuman Special Sections of the IEEE Transactions on Instrumentation and Measurement in the area of VLSI Testing, first in October 2003 (Innovations in VLSI Test Equipments), and then in October 2005 and April 2006 (Future of Semiconductor Test). Dr Das is the founding Editor-in-Chief of the International Journal of Computers, Information Technology and Engineering being published by Serials Publications, Delhi, India.
Dr Das edited jointly with P. K. Srimani a book entitled, Distributed Mutual Exclusion Algorithms, published by the IEEE Computer Society Press. Los Alamitos, CA 1992 in its Technology Series. He is also the author jointly with C. L. Sheng of a text on Digital Logic Design to be published by Ablex Publishing Corporation.
Dr Das is a Fellow of the Institute of Electrical and Electronics Engineers (IEEE), Inc. (with separate membership in the IEEE Computer Society, IEEE Systems, Man, and Cybernetics Society, IEEE Circuits and Systems Society, and IEEE Instrumentation and Measurements Society), and a Member of the Association for Computing Machinery (ACM), U.S.A. He was elected a Fellow of the IEEE in 1994 for contributions to switching theory and computer design.
Dr Das is the 1996 recipient of the IEEE Computer Society's highly esteemed Technical Achievement Award for his pioneering contributions in the fields of switching theory and modern digital design, digital circuits testing, microarchitecture and microprogram optimization, and combinatorics and graph theory. He is also the 1997 recipient of the IEEE Computer Society's Meritorious Service Award for excellent service contributions to IEEE Transactions on VLSI Systems and the Society, and was elected a Fellow of the Society for Design and Process Science, U.S.A. in 1998 for his accomplishments in integration of disciplines, theories and methodologies, development of scientific principles and methods for design and process science as applied to traditional disciplines of engineering, industrial leadership and innovation, and educational leadership and creativity. In recognition as one of the distinguished core of dedicated volunteers and staff whose leadership and services made the IEEE Computer Society the world's preeminent association of computing professionals, Dr Das was made a Golden Core Member of the Computer Society in 1998. Besides, Dr Das is the recipient of the IEEE Circuit and Systems Society's Certificates of Appreciation for services rendered as Associate Editor, IEEE Transactions on Very Large Scale Integration Systems, during 1995-1996 and during 1997-1998, and of the IEEE Computer Society's Certificates of Appreciation for services rendered to the Society as Member of the Society's Fellow Evaluation Committee, once in 1998 and then in 1999. Dr Das served as a Member of the IEEE Computer Society's Fellow Evaluation Committee for 2001 as well. He was elected a Fellow of the Canadian Academy of Engineering in 2002 for pioneering contributions to computer engineering research – specifically in the fields of switching theory and computer design, fault-tolerant computing, microarchitecture and microprtogram optimization, and to some problem areas in applied theory of graphs and combinatorics. Dr Das was elected a Fellow of the Engineering Institute of Canada in 2005 for exceptional contributions to Engineering to Canada.
Dr Das is the recipient of the prestigious Rudolph Christian Karl Diesel Best Paper Award of the Society for Design and Process Science in recognition of the excellence of their paper presented at the Fifth Biennial World Conference on Integrated Design and Process Technology held in Dallas, TX during June 4-8, 2000. He is also the co-recipient of the IEEE's esteemed Donald G. Fink Prize Paper Award for 2003 for their paper published in the December 2001 issue of the IEEE Transactions on Instrumentation and Measurement.